With improvements in the performances of information processing apparatuses such as devices for communication backbones and servers, the data rates of transmission and reception of signals in and out of the devices are desired to be increased. For a receiving circuit, a so-called clock-and-data recovery (CDR) is desired, which determines transmitted data at an appropriate timing and recovers data and a clock. The clock-and-data recovery is achieved by detecting a phase difference between input data and a clock (sampling clock) that is used for sampling data, and adjusting the phase of the sampling clock based on the phase difference thus detected.
For example, a clock-and-data recovery circuit (CDR circuit) of a voltage controlled oscillator (VCO) type (or a phase locked loop (PLL) type) is known, which adjusts the phase of a sampling clock by adjusting a control voltage of a voltage controlled oscillator. As the voltage controlled oscillator, an LC voltage controlled oscillator is known, which is capable of high-frequency oscillations with a low noise (see, for example, International Publication Pamphlet No. WO2009/096413 and Japanese Laid-open Patent Publication No. 2004-356701). The LC voltage controlled oscillator generates a clock signal having an oscillation frequency according to an inductor and a capacitor. In addition, a communication semiconductor integrated circuit including a plurality of LC voltage controlled oscillators in a PLL circuit has been proposed (see, for example, Japanese Laid-open Patent Publication No. 2010-63054).
FIG. 14 illustrates a configuration example of a receiving circuit configured with two lanes through which to receive data in parallel. The receiving circuit illustrated in FIG. 14 includes: a first CDR circuit (CDR1) 1400-1 configured to receive input data DI1 and output output data DO1; and a second CDR circuit (CDR2) 1400-2 configured to receive input data DI2 and output output data DO2. Since the first CDR circuit 1400-1 and the second CDR circuit 1400-2 are configured and operate in the same manner, the first CDR circuit 1400-1 will be described as an example.
The first CDR circuit 1400-1 determines whether the input data DI1 is “0” or “1” by use of a comparator circuit (determination circuit) 1401, and outputs the result of the determination as output data DO1. The comparator circuit (determination circuit) 1401 uses an output clock CK1 of an LC voltage controlled oscillator (LC VCO) 1405 as a sampling clock, and makes the determination on the input data DI1 at the timing of the clock CK1.
A phase-frequency detector circuit (PFD) 1402 detects a phase difference and a frequency difference between the input data DI1 and the clock CK1, and outputs an up signal UP1 and a down signal DN1 in accordance with the result of the detection.
A charge pump circuit (CP) 1403 and a loop filter (LPF) 1404 generate a control voltage VCOC1 by performing addition or subtraction of a current (injection or extraction of electric charges) in accordance with the up signal UP1 and the down signal DN1 outputted from the phase-frequency detector circuit 1402. The LC voltage controlled oscillator 1405 generates a clock having an oscillation frequency according to the control voltage VCOC1, and outputs the clock as an output clock CK1. With the above-described operation, the output clock CK1 of the LC voltage controlled oscillator 1405 is locked to the input data DI1, so that the function of the clock-and-data recovery is achieved.
A receiving circuit having a plurality of lanes, which receives a plurality of pieces of data and outputs a plurality of pieces of data in parallel through a plurality of CDR circuits, is generally implemented by arranging circuits of the respective lanes in parallel. If LC voltage controlled oscillators included in the CDR circuits of the respective lanes are arranged adjacent to each other, interference occurs between the LC voltage controlled oscillators due to mutual coupling of inductors of the LC voltage controlled oscillators. This interference causes injection locking, by which the phases of the clocks of the LC voltage controlled oscillators which are oscillating at nearby frequencies are shifted such that the outputs of the LC voltage controlled oscillators have the same phase and frequency.
When interference occurs between the LC voltage controlled oscillators in the loops of the CDR circuits, the phases of the LC voltage controlled oscillators are shifted in directions that make the phase difference between their output clocks smaller as indicated in FIG. 15, thus causing a phase error. A large interference between the LC voltage controlled oscillators relative to the loop gain of the CDR circuit causes a large phase error, leading to deterioration in the characteristics of the CDR circuit. In FIG. 15, a clock CK1 indicates a clock to be locked to input data DI1 while a clock CK2 indicates a clock to be locked to input data DI2. In addition, regarding the clocks CK1, CK2, dotted lines indicate an example of a case where there is no interference between the LC voltage controlled oscillators while solid lines indicate an example of a case where the phases are shifted by interference between the LC voltage controlled oscillators.
FIGS. 16A to 16C indicate influences of interference between LC voltage controlled oscillators. Each of the diagrams indicates a relation between an input phase difference θin_d/2π (corresponding to the phase difference between the input data DI1 and DI2 in the example illustrated in FIG. 14) and a clock phase difference θd/2π (corresponding to the phase difference between the clocks CK1 and CK2 in the example illustrated in FIG. 14). Each CDR circuit is controlled such that the clock is conformed to the phase of the input data. Accordingly, the input phase difference and the clock phase difference are ideally converged and equalized.
In a case where there is no interference between the LC voltage controlled oscillators included in the CDR circuits, the input phase difference and the clock phase difference are equalized as indicated in FIG. 16A. However, in a case where there is interference, a convergence phase error occurs as indicated in FIGS. 16B and 16C. Moreover, even in the case where there is interference between the LC voltage controlled oscillators included in the CDR circuits, no convergence phase error occurs when the input phase difference takes 0 or π, while a convergence phase error occurs when the input phase difference takes another value, as indicated in FIGS. 16B and 16C. In other words, this phase error varies depending on the magnitude of the input phase difference (the phase difference between input data) and on the magnitude of the interference between LC voltage controlled oscillators.
Increasing the loop gains of the CDR circuits allows for reducing the influence of interference between the LC voltage controlled oscillators, but changes the characteristics of the CDR circuits. In addition, since the loop gain of a CDR circuit is generally defined in its standards and has an optimum magnitude fixed in view of its performance, it is difficult to simply increase the loop gains of the CDR circuits.
For these reason, the LC voltage controlled oscillators (CDR circuits) are desirably implemented at a sufficient distance to reduce the influence of the interference, and are thus difficult to implement at a high density.